Power MOS devices, such as, for example, lateral diffused MOS (LDMOS) devices, are employed in a wide variety of applications, such as, for example, power amplification, switching, etc. In applications where high-frequency operation is desired, such as in a radio frequency (RF) range (e.g., above about 1 gigahertz (GHz)), a conventional LDMOS device generally uses a shorter gate length, in comparison to the gate length of a typical LDMOS device that is not adapted for high frequency applications, in order to improve the RF performance of the device. When operating the device in the RF frequency range, a shorter gate length is generally necessary for achieving a high input impedance. However, reducing the gate length undesirably increases hot-carrier induced (HCI) degradation in the device. Reducing the gate length also increases the gate resistance (Rg) associated with the device. Since the output gain of the MOS device is inversely proportional to the gate resistance of the device, increasing the gate resistance results in a decrease in the output gain of the device, which is particularly undesirable in an amplifier application. Moreover, there is presently no known mechanism by which an LDMOS device is able to protect itself from an over-power condition that places the device outside a safe operating area (SOA) of the device, thus resulting in a catastrophic failure of the device.
HCI degradation in an MOS device generally results from heating and subsequent injection of carriers into a surface oxide layer of the device, which results in a localized and nonuniform buildup of interface states and oxide charges near and underneath the surface oxide in a gate and/or drift region of the device. This phenomenon can produce undesirable variations in certain characteristics of the MOS device, including on-state resistance, transconductance, drain current, etc., thus impacting the performance and/or reliability of the device. It is well known that HCI degradation is a strong function of electric field distributions within the MOS device. While the lateral electric field near the gate in a drain side of the device is primarily responsible for heating and avalanche, the transverse electric field primarily influences carrier injection into the gate oxide. The reduction of channel length in the MOS device affects the internal electric field distributions, and hence the carrier heating and injection processes. As device geometries shrink, the localized internal electric field distributions can become even higher in the device, thus exacerbating the problem.
It is well known that HCI degradation in an LDMOS device can be reduced by decreasing an impurity doping concentration in a drift region of the device and/or employing a field plate for shielding the gate of the device. However, decreasing the doping concentration of the drift region also undesirably increases an on-state resistance of the device. Additionally, employing a field plate in the LDMOS device to reduce HCI degradation also undesirably increases an input capacitance of the device, due at least in part to an overlap of the field plate on the gate. The increase in input capacitance of the LDMOS device often significantly degrades the high-frequency performance of the device, so as to lessen any beneficial reduction in HCI degradation which may be achieved as a result of the field plate.
There exists a need, therefore, for an MOS device having improved high frequency performance, such as power gain and efficiency, and/or reliability, that does not suffer from one or more of the problems exhibited by conventional MOS devices. It would also be advantageous if the MOS device provided an internal self-protection mechanism for preventing device failure during an over-power condition. Moreover, it would be desirable if the improved MOS device was compatible with existing integrated circuit (IC) fabrication process technologies.